Semiconductor industry is now transitioning from 2D transistors, which are often planar, to 3D transistors having a three-dimensional gate structure. In 3D gate structures, the channel, source and drain are raised out of the substrate and the gate electrode is then wrapped around the channel on three sides (surfaces). The goal is to constrain the current to the raised channel, and abolish any path through which electrons may leak. In addition, the gate electrode controls the channel more effectively because it extends over more than one side of the channel. One such type of 3D transistor is known as FinFET (Fin field-effect transistor), in which the channel connecting the source and drain is a thin “fin” jutting out of the substrate. This results in the current being constrained to the channel, thereby preventing electrons from leaking.
For a FinFET transistor including a plurality of semiconductor fins (multi-fin FinFET), the parasitic capacitance inherently created between the source/drain regions and the gate electrode is increased significantly as compared to conventional planar FETs. The parasitic capacitance adversely affects the performance of the integrated circuits, limiting the frequency response of the device. Therefore, there is a need in the art for a method to form an improved multi-fin FinFET transistor with reduced parasitic capacitance.